Output buffer for +3.3 V applications in a 180 nm +1.8 V CMOS technology
Crossref DOI link: https://doi.org/10.3103/S0735272717110061
Published Online: 2017-12-24
Published Print: 2017-11
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Mahendranath, B.
Srinivasulu, Avireni http://orcid.org/0000-0001-6254-7990
License valid from 2017-11-01