An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic
Crossref DOI link: https://doi.org/10.35940/ijeat.C5311.029320
Published Online: 2020-02-28
Update policy: https://doi.org/10.35940/beiesp.crossmarkpolicy
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Paulchamy, B.
Kalpana, K.
Jaya, J.
