High speed VLSI Squaring unit of Binary Numbers Design with Yavadunam Sutra and Bit Reduction
Crossref DOI link: https://doi.org/10.35940/ijitee.B6879.129219
Published Online: 2019-12-30
Update policy: https://doi.org/10.35940/beiesp.crossmarkpolicy
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Bhavani*, K Durga
Lakshmi, N V V N J Sri
Sai, M Venkat
Teja, G D Sai