Testing and Diagnosis of Delay Faults in Finfet VLSI Circuits using Non-Incremental Genetic Algorithm
Crossref DOI link: https://doi.org/10.35940/ijitee.B7841.129219
Published Online: 2019-12-30
Update policy: https://doi.org/10.35940/beiesp.crossmarkpolicy
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Rayudu*, K.V.B.V
Jahagirdar, D R
Rao, Dr P Srihari
