Document is current

Any future updates will be listed below

A Layout Technique to Reduce the Impact of Parasitic Capacitors Within A Capacitor Array on the Nonlinearity of Data Converters

Crossref DOI link: https://doi.org/10.35940/ijitee.I7634.078919

Published Online: 2019-07-30

Update policy: https://doi.org/10.35940/beiesp.crossmarkpolicy

About CrossMark