Modeling and Design of Cascaded h-bridge type multi-level Inverters up to Thirty-one level for the Reduction and Performance Improvement
Crossref DOI link: https://doi.org/10.35940/ijrte.A2739.079220
Published Online: 2020-07-30
Update policy: https://doi.org/10.35940/beiesp.crossmarkpolicy
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Teja, K.Ravi
Ananth, D.V.N.
Rao, G. Joga