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Design & Implementation of Approximate 7:2 Compressor Based 16-bit Dadda Multiplier using Verilog

Crossref DOI link: https://doi.org/10.35940/ijrte.A7570.0512123

Published Online: 2023-05-30

Update policy: https://doi.org/10.35940/beiesp.crossmarkpolicy

Authors

,

Satyanarayana, P V V http://orcid.org/0009-0001-6971-1391
Venkanna, M. http://orcid.org/0009-0007-3966-7995
,

Jayasri, S. http://orcid.org/0009-0006-6567-5502
,

Kalyani, J. Vasavi http://orcid.org/0009-0007-0496-5706
,

Ramjee, B. http://orcid.org/0009-0002-4547-4253
,
More Information

Funding

: No, We did not receive.

Conflicts of Interest

: No conflicts of interest to the best of our knowledge.

Ethical Approval and Consent to Participate

: No, the article does not require ethical approval and consent to participate with evidence.

Availability of Data and Material

: (ieeexplore.ieee.org) and scholor.google.com

Authors Contributions

: I (M.Venkanna) have completed this paper work under the guidance of Sri P V V Satyanarayana Sr. Asst. Professor, Sri Vasavi Engineering College.