Delay Minimization in on Chip Interconnects by the Method of Logical Effort
Crossref DOI link: https://doi.org/10.35940/ijrte.D5242.118419
Published Online: 2019-11-30
Update policy: https://doi.org/10.35940/beiesp.crossmarkpolicy
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Sivasankari*, S.A.
Kumar, B.Sakthi
Vel, R.Ohmsakthi
