Design of Hybrid LUT/MUX FPGA Logic Architecture for size Reduction and Performance Improvement in FPGA
Crossref DOI link: https://doi.org/10.35940/ijitee.L3491.1081219
Published Online: 2019-10-30
Update policy: https://doi.org/10.35940/beiesp.crossmarkpolicy
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Aruna*, V.
Srigiri, Ch.
